The present invention generally relates to fabrication of semiconductor devices and more particularly to a fabrication process of a semiconductor device having an interconnection structure including a conductive plug filling a contact hole.
In semiconductor devices and integrated circuits that include a multilayer interconnection structure, a lower conductor pattern provided on a substrate is connected to an upper conductor pattern provided above the lower conductor pattern via a conductive plug filling a contact hole formed in an intervening interlayer insulation film.
When forming such a multilayer interconnection structure, an interlayer insulation film is provided so as to cover a lower conductor pattern formed on a substrate, followed by a process of formation of contact holes in the interlayer insulation film thus provided. Next, the contact holes are filled with a conductive material to form conductive plugs, and an upper conductor pattern is provided on the interlayer insulation film in electrical connection with the conductive plugs thus formed.
FIGS.1A-1D show a conventional process for forming such a multilayer interconnection structure on a Si substrate 1.
Referring to FIG. 1A, a first layer metal pattern 2 is provided on the Si substrate 1, and an interlayer insulation film 3 is provided thereon such that the interlayer insulation film 3 covers the first layer metal pattern 2. Further, the interlayer insulation film 3 is provided with contact holes 4 exposing the first layer conductor pattern 2, together with other through holes 4a acting as an alignment mark.
Next, in the step of FIG. 1B, a conductor layer 5 is deposited on the structure of FIG. 1A such that the conductor layer 5 fills the contact holes 4 as well as the holes 4a, and the structure thus formed is subjected to an etch back process as indicated in FIG. 1C, in which the conductor layer 5 is removed by an RIE process applied substantially vertically to the layer 5, leaving behind conductor plugs 7 filling the contact holes 4 or the through holes 4a. Thereby, the RIE process is carried out slightly excessively such that no conductor material is left on the upper major surface of the interlayer insulation film 3. As a result of such an excessive etching, the top surface of the plug 7 is located at a level slightly lower than the upper major surface of the interlayer insulation film 3 as indicated by a recess 6.
Next, in the step of FIG. 1D, a conductor layer is deposited on the structure of FIG. 1C such that the conductor layer fills the contact holes 4 or the through hole 4a now partially filled by the conductor plug 7, wherein the conductor layer thus deposited establishes an electrical contact with the plugs 7 thus filling the holes 4 or 4a. In the step of FIG. 1D, the conductor layer is patterned further to form an upper conductor pattern or interconnection pattern 8.
In such a conventional process of forming a multilayer interconnection structure, there arises a problem, associated with the formation of the depression 6 in the contact hole 4, in that the reliability of electrical connection is poor at the contact between the upper interconnection pattern 8 and the conductive plug 7. Further, because of the filling of the through hole 4a by the plug 7, the alignment mark appearing on the upper major surface of the conductor pattern 8 in correspondence to the through hole 4a is substantially obscured.
In order to improve the reliability of the electrical contact, there is a proposal to planarize the structure of FIG. 1C by employing a chemical mechanical polishing (CMP) process as indicated in FIG. 2A (e.g., Beyer et al., U.S. Pat. No. 4,944,836), wherein the upper major surface of the interlayer insulation film 3 is polished, in the structure of FIG. 2A, to form a flush surface with the top surface of the conductive plugs 7. After the planarization process of FIG. 2A, a conductor layer is deposited on the planarized upper major surface of the insulation film 3 and patterned subsequently. Thereby, the conductor pattern 8 is formed as indicated in FIG. 2B.
In the process of FIGS. 2A and 2B, the problem of formation of the recess 6 is eliminated and the reliability of electrical contact at the contact holes 4 is improved. However, such a CMP process completely eliminates the alignment mark that appears on the upper major surface of the conductor pattern 8 in correspondence to the through holes 4a.
Further, in view of possible alignment error at the time of exposure and patterning, there is a possibility that both of the process of FIGS. 1A-1D and the process of FIGS. 2A and 2B cause an excessively increased current density at the part where the conductor pattern 8 contacts the conductive plug 7, as indicated in FIGS. 3A and 3B.
Referring to FIG. 3A showing the structure of FIG. 1D or FIG. 2B in a plan view, it will be noted that the conductor pattern 8 and the conductive plug 7 of a rectangular cross section cause a contact at the hatched region, wherein it will be noted in FIG. 3A that the conductor pattern 8 and the conductive plug 7 cause an overlap in the hatched region. In such a contact structure, a deviation at the time of the exposure of only 0.1 .mu.m in the diagonal direction, as indicated in FIG. 3A by an arrow, causes a severe decrease of the contact area. In such a case, it should be noted that the contact area of FIG. 3A is represented as (x-0.1/.sqroot.2).sup.2, wherein x represents the length of the edge of the conductive plug 7. The foregoing relationship indicates that the alignment error causes a serious effect on the area of the contact and hence the current density, particularly in the case where the size of the plug as represented by the edge length x, is small.
In extremely fine semiconductor patterns such as the pattern of submicron devices, it is known that the corners of the rectangular patterns are rounded as a result of diffraction of exposure beam, even when a rectangular mask pattern is used for the exposure. Thus, in the actual submicron devices, the conductive plug is more closely approximated by a cylinder having a circular cross section than a rectangular block having a rectangular cross section.
FIG. 3B evaluates the effect of alignment error for the case where two conductive plugs, each having a circular cross section in the plan view, are contacted.
In such a case, the area of the contact, represented in FIG. 3B by hatching, is represented as EQU 2{2.pi.r.sup.2 .multidot.cos.sup.-1 (y/2r)/360-(2/y)r.multidot.sin (cos.sup.-1 (y/2r))}
where r represents the radius of the circular cross section of the plug, while y represents the deviation of the pattern caused by the alignment error.
For example, the contact area reduces to 77.7% of the nominal contact area for the plug having a radius r of 0.4 .mu.m, when there exists an alignment error y of 0.1 .mu.m. Further, the reduction of the contact area appears more significantly in the plugs of smaller diameters.
When the contact area is reduced as such, the current density increases as noted before, while such an increase in the current density in turn tends to invite failure of the contact by electromigration effect or by stress migration effect, and the lifetime of the contact is reduced substantially.
In order to avoid the problem of steep decrease of the contact area caused by the alignment error, one may form the conductive plugs such that each conductive plug protrudes in the upward direction from the upper major surface of the interlayer insulation film. By providing an conductor pattern on such an interlayer insulation film, it is possible to cause the conductor pattern to contact not only with the top surface of the conductive plug but also with the exposed side walls thereof. Thereby, the area of contact is increased substantially even in the case the upper conductor pattern contacts with only a part of the top surface of the conductive plug due to the alignment error.
As a method of forming a conductive plug such that the conductive plug protrudes from the upper major surface of an interlayer insulation film, the U.S. Pat. No. 5,244,534 describes the use of a CMP process including a first CMP step for polishing away a conductor layer from the upper major surface of the interlayer insulation film and a second CMP step for polishing the exposed upper major surface of the interlayer insulation film.
However, the process of the foregoing prior art reference is difficult to use in practice, particularly with regard to the selection of an appropriate abrasive slurry and setting of an appropriate polishing condition for the second polishing step. Thereby, the foregoing process is somewhat unpredictable and cannot be used for the production of semiconductor devices.